The present invention relates generally to electronic musical instruments, such as electronic organs. More specifically, the invention concerns methods and circuits employed in such instruments for interfacing the key and tab switches thereof with a suitably programmed general purpose microprocessor.
General purpose microprocessor chips are being employed in electronic apparatus intended for the consumer market at an ever increasing rate largely as a result of the dramatic cost reduction in these chips over the past few years. For example, electronic organ manufacturers are beginning to use these low cost microprocessor chips to perform many functions heretofore necessitating the use of large amounts of relatively costly hard-wired logic circuits. As a result, many features previously available only on higher priced electronic organs are now being found on lower cost models.
However, in order to make the most efficient use of the computational capabilities of the microprocessor, it has been found necessary to provide an interface between the microprocessor and the player manipulable inputs to the organ. These player manipulable inputs include key and pedal switches which control the pitch of the generated audio signals as well as various other switches such as tab, toggle, or pushbutton switches (all of which will hereafter be collectively referred to as tab switches) which control the voicing circuits of the organ as well as various automatic features such as automatic rhythm accompaniment. In order to couple data from the operated key and tab switches, a time multiplexed scanning technique is frequently employed whereby the switches are sequentially scanned in response to a sequentially incremented multibit scan control signal for generating a serial data signal composed of a series of consecutive time slots each corresponding to one of the scanned switches. The development of a logical 1 signal in a particular time slot represents the depression or operation of the corresponding switch while a logical 0 signal indicates that the switch is not depressed or operated. U.S. Pat. No. 3,929,051 to Moore, which is incorporated herein by reference, is exemplary of such scanning systems. It has been determined that most currently available general purpose microprocessor chips are not operable at sufficiently fast rates, considering the many other computational operations which must be performed, to adequately accomplish this scanning operation. Therefore, it would be highly desirable to provide a circuit interfacing between the player manipulable switches of the organ and the microprocessor for performing the scanning operation. In addition, since the microprocessor is responsive to input data in parallel form, means must be provided to convert the serial data indentifying an operated switch to a parallel signal having a corresponding value. Also, it would be desirable to debounce the input serial data before transferring the corresponding parallel data to the microprocessor to provide a high degree of confidence that the data is valid.
The present invention provides a serial interface circuit capable of realizing the foregoing functions and which processes the serial data produced by key switches in a different manner from the serial data produced by the tab switches to minimize required memory capacity. More specifically, the interface circuit of the invention comprises a plurality of sequentially operated logic components including a set of registers operated thereby and a random access memory (RAM). Serial data representing operated key switches is coupled to the interface circuit in response to the development of an output scan control signal and is converted to multibit signals each representing the time encoded position of a depressed key. The multibit signals are stored in consecutive memory locations in a first section of the RAM in a compressed format. That is, if a depressed key is released, the memory location previously occupied by its corresponding multibit signal is replaced with a multibit signal corresponding to a depressed key so that, beginning from the initial memory location of the first section of the RAM, data continues to be stored in consecutive memory locations. The multibit signals representing depressed keys are transferred to the microprocessor from the RAM only after three scans of the key and tab switches has been completed, namely; two consecutive scans representing identical serial data immediately preceded by a scan representing different serial data. As a result, a level of confidence is achieved that valid data is being read into the microprocessor which was generated in response to key and tab switch depressions and not in response to switch bounce. Serial data representing operated tab switches is stored in a second section of the RAM. In particular, each tab switch is represented by a single bit of an eight bit stored word, a logical 1 bit representing an operated tab switch and a logical 0 bit representing an undepressed tab switch. In response to the debounce criteria described above being satisfied, each eight bit word is sequentially transferred from the RAM to the microprocessor. The RAM includes a third section for storing data transferred thereto from the microprocessor. This data is converted by the interface circuit to a serial form which can be used for controlling various circuits of the organ.